A NEW APPROACH OF AN ERROR DETECTING AND CORRECTING CIRCUIT BY ARITHMETIC LOGIC BLOCKS

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

Evaluation of Students’ Achievement in the Final Exam Questions for Microelectronic (KKKL3054) using the Rasch Model

AbstractThe assessment of the students in KKKL3054 Microelectronic includes PBL (20%), quizzes (10%), midterm exam (20%), tutorial (10%), and final exam (40%). In this paper, we discuss the performance of the students’ achievement in the final examination. By using the Rasch model, the students’ performance based on the difficulty level of each question, can be assessed. Each question is mapped to the number of students who are able to answer the question correctly. Results from the 17 students assessed, answering 15 questions of the final examination, showed that the distribution of the ability of each student answering questions from different levels of difficulty are fairly distributed. Findings from this evaluation can help us improve the course content as well as the course outcomes. We can conclude that by using the Rasch model, the ability of each student answering the final exam questions can be evaluated

GA-based Optimisation of a LiDAR Feedback Autonomous Mobile Robot Navigation System

Autonomous mobile robots require an efficient navigation system in order to navigate from one location to another location fast and safe without hitting static or dynamic obstacles. A light-detection-and-ranging (LiDAR) based autonomous robot navigation is a multi-component navigation system consists of various parameters to be configured. With such structure and sometimes involving conflicting parameters, the process of determining the best configuration for the system is a non-trivial task. This work presents an optimisation method using Genetic algorithm (GA) to configure such navigation system with tuned parameters automatically. The proposed method can optimise parameters of a few components in a navigation system concurrently. The representation of chromosome and fitness function of GA for this specific robotic problem are discussed. The experimental results from simulation and real hardware show that the optimised navigation system outperforms a manually-tuned navigation system of an indoor mobile robot in terms of navigation time

Strengthening programming skills among engineering students through experiential learning based robotics project

This study examined the educational effects in strengthening programming skills among university’s undergraduate engineering students via integration of a robotics project and an experiential learning approach. In this study, a robotics project was conducted to close the gap of students’ difficulty in relating the theoretical concepts of programming and real-world problems. Hence, an experiential learning approach using the Kolb model was proposed to investigate the problem. In this project, students were split into groups whereby they were asked to develop codes for controlling the navigation of a wheeled mobile robot. They were responsible for managing their group’s activities, conducting laboratory tests, producing technical reports and preparing a video presentation. The statistical analysis performed on the students’ summative assessments of a programming course revealed a remarkable improvement in their problem-solving skills and ability to provide programming solutions to a real-world problem

Design of a band-pass filter in 0,18 μm CMOS for 2,4 GHz reader-less RFID transponder

Sustavi temeljeni na Radio Frequency Identification (RFID) sada su široko rasprostranjeni. Pojasno fazni filtri igraju važnu ulogu u funkcioniranju RFID transpondera. U ovom radu, pojasno fazni filtar s induktorom aktivnim samo s tranzistorom prikazan je za kompaktni RFID transponder bez čitača visokih performansi. Rezultat simulacije rasporeda otkriva da središnja frekvencija filtra može biti postavljena na frekvenciju od 2,42 GHz sa širinom pojasa od 38 MHz. Jezgra filtra zauzima površinu od 0,004 mm2 i gubi samo 1,3 mW kod napona napajanja od 1,5 V. Predloženi filtar dizajniran je pomoću CEDEC 0,18 μm CMOS tehnologije u Mentor Graphics okruženju.Radio Frequency Identification (RFID) based systems are ubiquitous nowadays. Band pass filters always play an important role in overall performance of an RFID transponder. In this paper, a band pass filter with a transistor only active inductor is presented for compact high performance reader-less RFID transponder. Post layout simulation result reveals that the centre frequency of the filter can be set to 2,42 GHz frequency with a bandwidth of 38 MHz. The filter core occupies an area of 0,004 mm2 and dissipates only 1,3 mW at 1,5 V supply voltage. CEDEC 0,18 μm CMOS technology in Mentor Graphics environment has been used for the design of the proposed filter

A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area

Dynamic Residential Energy Management for Real-Time Pricing

A home energy management system (HEMS) was designed in this paper for a smart home that uses integrated energy resources such as power from the grid, solar power generated from photovoltaic (PV) panels, and power from an energy storage system (ESS). A fuzzy controller is proposed for the HEMS to optimally manage the integrated power of the smart home. The fuzzy controller is designed to control the power rectifier for regulating the AC power in response to the variations in the residential electric load, solar power from PV panels, power of the ESS, and the real-time electricity prices. A self-learning scheme is designed for the proposed fuzzy controller to adapt with short-term and seasonal climatic changes and residential load variations. A parsimonious parameterization scheme for both the antecedent and consequent parts of the fuzzy rule base is utilized so that the self-learning scheme of the fuzzy controller is computationally efficient

A rapid and non-destructive technique in determining the ripeness of oil palm fresh fruit bunch (FFB)

Oil palm industry is one of the main industries in Malaysia that contributes to the country’s gross domestic product (GDP). In the oil palm industrial sector, methods of planting, detection and assessment are very important to produce high quality palm oil. Currently, the ripeness of oil palm fresh fruit bunch (FFB) is estimated using eyesight (most common), computer vision, hyperspectral imaging, light detection and ranging (LiDAR), near infrared (NIR) spectroscopy, and magnetic resonance imaging. The objective of this research is to introduce a rapid and non-destructive technique in determining and assessing the ripeness of oil palm fresh fruit bunch (FFB) by using a LiDAR scanning system. The LiDAR scanning system is used to scan three types of oil palm fruits at different level of ripeness which is under ripe, ripe, and over ripe. The reflectance intensity that bounces off the fruits are gathered and analysed to determine the different level or ripeness. Even though the intensity value is purely relative, it is proportional to the reflectance or absorption rate from the LiDAR sensor. A rapid method to determine the ripeness of palm fruits using a LiDAR sensor was proposed by calculating the reflectance percentage from 0% to 100% using the concept of linearity

DESIGN OF A LOW-POWER AND HIGH THROUGHPUT ERROR DETECTION AND CORRECTION CIRCUIT USING THE 4T EX-OR METHOD

This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41%) and high throughput (95.20%)

Single core hardware module to implement partial encryption of compressed image

Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested